The invention is based on a circuit arrangement for operating a synchronous motor of the type defined in the preamble of claim 1 and including a multi-phase armature winding in a direct voltage network.
In a known circuit arrangement of this type for a three-phase synchronous motor (DE 3,940,569) the switching signals are configured, in order to reduce commutation noise and radio interference, so that the two switching signals for the semiconductor switches associated with the commutating winding phases overlap one another in time. In the overlap region, one of the two switching signals is clocked in such a way that the average of the phase current increases in the up-commutating winding phase and decreases in the down-commutating winding phase, namely linearly or according to an exponential function. However, this type of commutation requires relatively high expenditures for circuitry.